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A Verified Pipeline Framework for Certifiable AI Robustness

OLIVEIRA, S. B.; Lima Filho, E. B.; CORDEIRO, L. C

2026 • IEEE 2nd International Conference on Consumer Technology

Resumo

Artificial intelligence models often perform well on curated datasets but may fail under real-world perturbations, an aspect that has the potential to hinder practical applications. In that sense, conventional robustness evaluations help expose such weaknesses and then minimize field problems. However, they offer no guarantee of testing correctness. As a response, we propose the smart inference pipeline with verification (SIP-V), which addresses such limitations by formally verifying robustness evaluation pipelines rather than models themselves. It encodes perturbation rules as logical constraints and employs multiple satisfiability modulo theories solvers, at runtime, to verify preconditions and postconditions on data, label, and parameter transformations. By experimenting on benchmark datasets and representative models, we demonstrated consistent detection of injected violations and full validation of compliant cases, with average execution times of 0.24 s, using cooperating validity checker number 5, and 9.9 s, using Z3. Indeed, by integrating empirical testing with formal reasoning, SIP-V establishes a practical foundation for certifiable and auditable AI robustness.

palavras-chave

Palavras-chave

AI robustnessformal verificationsatisfiability modulo theoriesSMT solverslogical constraintscertified robustnessauditable AIruntime verificationpreconditions and postconditions

Status

Published

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